Blind equalization of time errors in a time-interleaved ADC system
نویسندگان
چکیده
منابع مشابه
Equalization of Time Errors in Time Interleaved ADC System -- Part I: Theory, Report no. 2494
To significantly increase the sampling rate of an A/D converter (ADC), a time interleaved ADC system is a good option. The drawback of a time interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In t...
متن کاملBlind Adaptive Equalization of Mismatch Errors in Time Interleaved A/D Converter System, Report no. 2486
To significantly increase the sampling rate of an A/D converter (ADC), a time interleaved ADC system is a good option. The drawback of a time interleaved ADC system is that the ADCs are not exactly identical due to errors in the manufacturing process. This means that time, gain and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In t...
متن کاملEqualization of Time Errors in Time Interleaved ADC System -- Part II: Analysis and Examples, Report no. 2495
In the accompanying paper a method for blind (i.e., no calibration needed) estimation and compensation of the time errors in a time interleaved ADC system was presented. In this paper we evaluate this method. The Cramer-Rao bound is calculated, both for additive noise and random clock jitter. Monte-Carlo simulations have also been done to compare to the CRB. Finally, the estimation method is va...
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High speed analog-to-digital converters capable of digitizing signals with bandwidths of several tens of GHz have applications in high-speed instrumentation, wideband radar and optical communications. However, the design of converters with such high input bandwidths is constrained by the need for wideband sample-and-hold circuits with sufficiently low clock jitter. A number of photonic sampling...
متن کاملA Timing Skew Calibration Scheme in Time-Interleaved ADC
This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital...
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ژورنال
عنوان ژورنال: IEEE Transactions on Signal Processing
سال: 2005
ISSN: 1053-587X
DOI: 10.1109/tsp.2005.843706